With the official announcement of the AMD Ryzen 5000 or Ryzen 4000 (AMD has not confirmed anything yet) around the corner, more information is already leaking, about the Vermeer platform powered by the Zen3 microarchitecture.

The latest information revealed that we will once again have a 16-core and 32-thread CPU as the company’s most powerful option with 512 KB of L2 cache per core up to a maximum of 4 MB of L2 cache, 32 MB L3 per CCD, and the surprise is that the platform will be able to handle up to 1 TB of DDR4 RAM @ 3200 MHz in Dual Channel configuration, plus it will also be compatible with ECC RAM.

Unlike the previous generation design, in which each CCD was composed of two CCX (Core Complexes), the CCD of the AMD Zen3 processors will conform to a single CCX that will have 8 cores and operate in both mode single thread (1T) and also in two thread mode (2T) for up to 16 threads per CCX. Since the chip houses a maximum of two CCDs, the number of cores and threads will be a maximum of 16 cores and 32 threads, which is the same configuration that we can find in the AMD Ryzen 9 3950X, the current top of the range CPU of the company.