An entry in SiSoft Sandra benchmarking software revealed configuration of two AMD EPYC Rome @ 1.40 GHz CPUs in the form of an engineering sample, since the final speed of this processor is set at 2.35 GHz.
Each of these CPUs feature 64 cores and 128 processing threads where each of the cores has 512 kB of dedicated L2 cache memory with each L3 cache memory per CCX is doubled, so that we have in total 16x 16 MB L3.
For each 64-core EPYC Rome CPU, there are a total of 8 chiplets. So, each of the 8-core chiplets features two 16 MB L3 cache slices This doubling in the L3 cache by CCX could help processors improve data transfers between the chipset and the dedicated die I / O @ 14nm located in the middle of the CCX. This is particularly important, since the die I / O controls the memory with its 8-channel DDR4 monolithic RAM controller.